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;� �
;� SYSTEM STARTUP FOR 68HC16-BASED DATA-LOGGER �
;� �
;� Copyright (c) 1995 by M. Lutfi �
;� �
;����������������������������������������������������������������������������ͼ
.PROCESSOR M68HC16
.external _main, __memory,__pdata
.external ._main, .__pdata
.external .__text__, .__data__, .__bss__
.public _exit, __stext
.include "hc16regs.mac"
.include "mcx16.mac"
.include "lgrset.mac"
.psect _text
__stext:
;*********** MCU INIT ******************
; These procedures handled by MCX-16
; Rewritten for clarity only
;**********************************
; ldab #0Fh
; tbek ; point EK to bank F for register access
; ldab #00H
; tbxk ; point XK to bank 0
; tbyk ; point YK to bank 0
; tbzk ; point ZK to bank 0
;
; ldaa #007Fh ; w=0, x=1, y=111111
; staa SYNCR ; set system clock to 16.78 mhz
;
; clr SYPCR ; turn cop (software watchdog) off,
; ; since cop is on after reset
; ldab #7FH
; stab SYNCR
; clr SYPCR
;
;****** init SRAM ******
; ldab #1
; std RAMBAH
; clrd
; std RAMBAL
; clr RAMMCR ;SRAM addr start from 0x10000 to 0x103FF
;****** init external RAM *******
ldd #00003 ; at reset, the csboot block size is 512k.
std CSBARBT ; this line sets the block size to 64k since
; that is what physically comes with the evb16
ldd #00303h
std CSBAR0 ;set U1 ram base addr to 0x30000: bank 3, 64k
std CSBAR1 ;set U3 ram base addr to 0x30000: bank 3, 64k
ldd #05030h ;no wait states
std CSOR0 ;set chip select 0, upper byte, write only
ldd #03030h
std CSOR1 ;set chip select 1, lower byte, write only
ldd #00303h
std CSBAR2 ;set chip select 2 to fire at base addr 0x30000
ldd #07830h
std CSOR2 ;set chip select 2, both bytes, read and write
ldd #03FFFh
std CSPAR0 ;set chip selects 0,1,2 to 16-bit ports
;�����������������������������������������������������������������������������
;� ADC INITIALIZATION �
;� Summary: �
;� The ADC module is mapped into 32 words of address space. Five words are �
;� control/status registers, one word is digital port data, and 24 words �
;� provide access to the results of ADC conversion (eight addresses for each �
;� type of converted data). Two words are reserved for expansion. �
;� The ADC module base address is determined by the value of the MODMAP bit �
;� int the system integration module configuration register (SIMMCR). �
;� The base address is normaly $FFF700 in the MC68HC16Z1. �
;� Internally, the ADC has both a differential data bus and a buffered �
;� IMB data bus. Registers not directly associated with AD conversion �
;� functions, such as the MCR, the MTR, and the PDR, reside on the bufferd �
;� bus, while conversion registers and result registers reside on the �
;� differential bus. �
;� �
;� Registers that must be set prior operation: �
;� ADMCR: �
;� STOP = 0 (normal operation) �
;� FRZ = 0 �
;� SUPV = 1 (supervisory mode) �
;� ADCTL0: �
;� PRS = 1 (ADC clock = system clock/4 = 16.667 MHz/4) �
;� STS = 0 (4 A/D clock periods in the sample time) �
;� RES10 = 1 (10-bit conversion) �
;� ADCTL1: �
;� SCAN = 1 (continuous conversion) �
;� MULT = 1 (sequential conversion of four or eight channels �
;� selected by [CD:CA]) �
;� S8CM = 1 (eight-conversion sequence) �
;� CD = 0 (measured data at each channel stored into his register) �
;� �
;�����������������������������������������������������������������������������;
ldd #0000h
std ADCMCR ;turn on ADC
ldd #0001h
std ADCTL0 ;10-bit, set sample period
;�����������������������������������������������������������������������������
;� �
;� SCI DRIVER INITIALIZATION �
;� �
;� 1. Sets up the SCI and starts an infinite loop of receive transmit �
;� 2. QSM configuration summary: �
;� * After reset, the QSM remains in an idle state, requiring initialization �
;� of several registers before any serial operations may begin execution. �
;� * The type of serial frame (8 or 9 bit) and the use of partiy must be �
;� determined by M. PE and PT. �
;� * For receive operation, WAKE, RWU, ILT, ILIE must be considered. �
;� The receiver must be enabled (RE) and, usually, RIE should be set. �
;� * For transmit operation, the transmitter must be enabled (TE) and, �
;� usually, TIE should be set. The use of wired-OR mode (WOMS) must also �
;� be decided. Once the transmitter is configured, data is not sent �
;� until TDRE and TC are cleared. To clear TDRE and TC, the SCSR read �
;� must be followed by a write to SCDR (either the lower byte or the �
;� entire word). �
;� * QIVR should be programmed to one of the user-defined vectors ($40-$FF) �
;� during initialization of the QSM. �
;� After reset, QIVR determines which two vectors in the exception vector �
;� table are to be used for QSM interrupts. The QSPI and SCI submodules �
;� have separate interrupt vectors adjacent to each other. �
;� Both submodules use the same interrupt vector which LSB: �
;� 1: interrupt generated by QSPI �
;� 0: interrupt generated by QSCI �
;�> Detail Configurations in QSM: �
;� * QMCR: �
;� STOP = 0 (Normal QSM clock operation) �
;� FRZ1 = 0 (Ignore the FREEZE signal on the IMB) �
;� SUPV = 1 (supervisor access) �
;� IARB = $A (priority = 10; $F = highest priority, used by timer) �
;� * QILR: �
;� ILQSPI = 1 (lowest priority) �
;� ILSCI = 7 (highest priority) �
;� QIVR = set to SCI interrupt handler's address �
;� �
;�����������������������������������������������������������������������������;
orp #INTS_OFF ; Turn off interrupts while enabling SCI
ldab #0Fh
tbek ; EK = F (K=$Fxxx)
ldd #008Ah
std QMCR ; Set IARB=10 for intermodule bus arbitration
ldd QILR ; Get content of QSM Interrupt Levels Register
anda #0E8h ; Clear out ILSCI field
oraa #SCIINTLV ; Set SCI interrupt level in ILSCI field
ldab #SCIINTV ; Load SCI Interrupt Vector #
std QILR ; Update QILR
ldd #RIE+RE+TE ; Receiver enabled with interrupts active,
; Transmitter enabled without interrupts,
; 1 Start Bit, 1 Stop Bit, 8 Data Bits
std SCCR1 ; Set up SCI operating conditions
ldd #BR9600 ; Set up 9600 baud rate
std SCCR0
;����������������������������������������������������������������������������
;� STACK ALLOCATION �
;� �
;� I M P O R T A N T S Y S T E M C O N F I G U R A T I O N N O T E: �
;� �
;� MCX-16 Requires locations $10000 through $1002F for internal operations. �
;� Begin the allocation of MCX-16 System Tables at an address equal to or �
;� greater than $10030. �
;����������������������������������������������������������������������������;
ldk #.__pdata ; select memory bank of _data
tbxk
tbyk
ldk #.__data__
tbzk
ldx #__pdata ; start of data descriptor
ldy 0,x ; start of data images
aix #2 ; next word
ibcl:
ldab 0,x ; flag
beq zbss ; nul, next step
bpl idad ; if segment
aix #2 ; move to it
ldab 0,x ; load it
tbzk ; in data pointer extension
idad:
ldz 1,x ; data address
ircl:
ldd 0,y ; transfert by word
std 0,z ; size must be even
aiy #2 ; next word
aiz #2
cpy 3,x ; end of block ?
blo ircl ; no, loop
aix #5 ; descriptor size
bra ibcl ; next block
zbss:
ldk #.__bss__
tbxk
tbek
tbyk
tbzk
tbsk
ldx #sbss ; start of bss
clrd ; to be zeroed
bra mtest ; start loop
bcl:
std 0,x ; clear memory
aix #2 ; next word
mtest:
cpx #__memory ; end of memory ?
blo bcl ; no, continue
; aix #4000H ; you can set-up a 4K stack
; txs ; above the BSS
lds #3FEh ; or directly initialize ptr
jsr _main,#._main
; call main routine of application
_exit:
bra _exit ; loop here if return
;
.end
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