; C STARTUP FOR 68HC16 UNDER MCX-16 REAL-TIME KERNEL
; ==================================================
; Copyright (c) 1995
; Designed and programmed by Muhammad Lutfi
; for Final Project (TA)
; Thesis Advisors:
; Dr. Ir. Farida Idealistina Muchtadi
; and Ir. Sutanto Hadisupadmo, M.T.
;
; Instrumentation and Controls Lab.
; Engineering Physics Dept.
; Institut Teknologi Bandung
; Jl. Ganesha 10
; Bandung 40132
; Phone: (022) 2504424 ext 759
; FACS: (022)2504424
;
;
;
; Platform : Microcontroller 68HC16Z1 on Evaluation Board (EVB)
;
; Summary:
; > Other initialization, except for QSM and ADC module, not necessarily
; done
; > Take care with heap an pre-initialized RAM initialization
;
.include "lgrset.mac"
.external _main, __memory,__pdata
.external ._main, .__pdata
.external .__text__, .__data__, .__bss__
.public _exit, __stext
.DEFINE STACK_SIZE = 1000H
.psect _bss ; stack section
sbss:
.psect _text ; program section
__stext:
;*********** MCU INIT ******************
; These procedures handled by MCX-16
; Rewritten for clarity only
; Still used in HARRAT version.
;***************************************
;
; ROM Start address: 0x00000 (program starts from 0x400 instead)
;
; BITS
; +--------------+--------------------------------+
; ! ! 2222 1111 1111 11 !
; ! ADDR PINS ! 3210 9876 5432 1098 7654 3210 !
; +--------------+--------------------------------+----------+
; ! ADDR[23..0] ! 0000 0000 0000 01?? ???? ????B != 0x00400 !
; ! ADDR[23..11] ! 0000 0000 0000 0xxx xxxx xxxxB != 0x00000 !
; +--------------+--------------------------------+----------+
;
; BLKSZ = 64 KB => address lines compared: ADDR[23..16]
;
; Frequency:
; FQ_SYSTEM = FQ_REF*(4^(y+1)*(2^((2*W) + x)))
; FQ_VCO = F_SYSTEM^(2-X)
;
.DEFINE BLKSZ = 011B
.DEFINE ADDR = 0000h
.SET CSBARBT_CFG = ((BLKSZ) | (ADDR << 3))
.DEFINE FQ_REF = 16780000 ; MHz
.DEFINE SW = 00B
.DEFINE SX = 01B
.DEFINE SY = 0111111B
.DEFINE
SEDIV = (0<<7),
SLIMP = (1<<4),
SLOCK = (1<<3),
RSTEN = (1<<2),
STSIM = (1<<1),
STEXT = 1
.SET SYNCR_CFG = ((SW<<7)|(SX<<6)|SY)
ldab #0Fh
tbek ; point EK to bank F for register access
ldab #00H
tbxk ; point XK to bank 0
tbyk ; point YK to bank 0
tbzk ; point ZK to bank 0
ldd #CSBARBT_CFG ; at reset, the csboot block size is 512k, so
std CSBARBT ; this line sets the block size to 64k since
; that is what physically comes with the EVB16
; Boot ROM starts from 0x400 to 0xFFFF
ldab #SYNCR_CFG
stab SYNCR ; set system clock to 16.78 mhz
NOT_L:
brclr SYNCR+1,#SLOCK,NOT_L ;wait until synthesizer lock bit is set
;
; SYPCR:
; �����������������������������������������������������������Ŀ
; � SWE = 0� SWP = 0� SWT = 11 � HME = 1 � BME = 0 � BMT = 00 �
; �������������������������������������������������������������
; SWE=0 : Watchdog disabled
; SWP=0 : Software watchdog clock not prescaled
; SWT[1:0]=11 : software watchdog timing
; HME=1 : enable halt monitor function
; BME=0 : disable bus monitor function for an internal to external bus cycle
; BMT=00 : 64 system clocks for bus monitor timing
;
.DEFINE
SWE = 0,
SWP = 0,
SWT = 011B,
HME=1,
BME=0,
BMT=0
.DEFINE SET_SYPCR = (BMT|(BME<<2)|(HME<<3)|(SWT<<4)|(SWP<<6)|(SWE<<7))
ldab #SET_SYPCR ;#38H
stab SYPCR ; turn cop (software watchdog) off,
; since cop is on after reset
.IF TOROM
ldd CSORBT
andd #0E7FFh ; R/W* = 00B, means that
ord #(01B<<11) ; ROM is read only
std CSORBT
.ENDIF
;************* Stack Allocation *************
.IF USE_EXT_RAM
ldk #2
tbsk ; set SK to bank 2 for system stack
lds #3FEh ; put SP at top of 1k internal SRAM (0x203FE)
.ELSE
ldk #1
tbsk ; set SK to bank 1 for system stack
lds #3FEh ; directly initialize ptr to use 0x103FE (SRAM)
.ENDIF ; and below as system stack
;�����������������������������������������������������������������������������Ŀ
;� ADC INITIALIZATION �
;� Summary: �
;� The ADC module is mapped into 32 words of address space. Five words are �
;� control/status registers, one word is digital port data, and 24 words �
;� provide access to the results of ADC conversion (eight addresses for each �
;� type of converted data). Two words are reserved for expansion. �
;� The ADC module base address is determined by the value of the MODMAP bit �
;� int the system integration module configuration register (SIMMCR). �
;� The base address is normaly $FFF700 in the MC68HC16Z1. �
;� Internally, the ADC has both a differential data bus and a buffered �
;� IMB data bus. Registers not directly associated with AD conversion �
;� functions, such as the MCR, the MTR, and the PDR, reside on the bufferd �
;� bus, while conversion registers and result registers reside on the �
;� differential bus. �
;� �
;� Registers that must be set prior operation: �
;� ADMCR: �
;� STOP = 0 (normal operation) �
;� FRZ = 0 �
;� SUPV = 1 (supervisory mode) �
;� ADCTL0: �
;� PRS = 00011B (ADC clock = system clock/8 = 2.1 MHz (Max ADC freq) �
;� STS = 00 (4 A/D clock periods in the sample time) �
;� RES10 = 01 (10-bit conversion) �
;� ADCTL1: �
;� SCAN = 1 (continuous conversion) �
;� MULT = 1 (sequential conversion of four or eight channels �
;� selected by [CD:CA]) �
;� S8CM = 1 (eight-conversion sequence) �
;� CDCA = 0xxx (measured data at each channel stored into his register) �
;� �
;�������������������������������������������������������������������������������
.DEFINE MY_PRS = 11B,
MY_STS = 00B,
MY_RES10 = 1
.DEFINE MY_CDCA = 1000B,
MY_S8CM = 1,
MY_MULT = 1,
MY_SCAN = 1
ldab #0Fh
tbek ; EK = F (K=$Fxxx)
ADCMCR_SET 0, 0, 0
ADCTL0_SET MY_PRS, MY_STS, MY_RES10
ADCTL1_SET MY_CDCA, MY_S8CM, MY_MULT, MY_SCAN
;�����������������������������������������������������������������������������Ŀ
;� �
;� SCI DRIVER INITIALIZATION �
;� �
;� 1. Sets up the SCI and starts an infinite loop of receive transmit �
;� 2. QSM configuration summary: �
;� * After reset, the QSM remains in an idle state, requiring initialization �
;� of several registers before any serial operations may begin execution. �
;� * The type of serial frame (8 or 9 bit) and the use of partiy must be �
;� determined by M. PE and PT. �
;� * For receive operation, WAKE, RWU, ILT, ILIE must be considered. �
;� The receiver must be enabled (RE) and, usually, RIE should be set. �
;� * For transmit operation, the transmitter must be enabled (TE) and, �
;� usually, TIE should be set. The use of wired-OR mode (WOMS) must also �
;� be decided. Once the transmitter is configured, data is not sent �
;� until TDRE and TC are cleared. To clear TDRE and TC, the SCSR read �
;� must be followed by a write to SCDR (either the lower byte or the �
;� entire word). �
;� * QIVR should be programmed to one of the user-defined vectors ($40-$FF) �
;� during initialization of the QSM. �
;� After reset, QIVR determines which two vectors in the exception vector �
;� table are to be used for QSM interrupts. The QSPI and SCI submodules �
;� have separate interrupt vectors adjacent to each other. �
;� Both submodules use the same interrupt vector which LSB: �
;� 1: interrupt generated by QSPI �
;� 0: interrupt generated by QSCI �
;�> Detail Configurations in QSM: �
;� * QMCR: �
;� STOP = 0 (Normal QSM clock operation) �
;� FRZ1 = 1 (Halt the QSM on a transfer boundary) �
;� FRZ0 = 0 �
;� SUPV = 1 (supervisor access) �
;� IARB = $A (priority = A; $F = highest priority, used by timer) �
;� * QILR: �
;� ILQSPI = 0 (disabled) �
;� ILSCI = 7 (highest priority) �
;� QIVR = set to SCI interrupt handler's address �
;� �
;�������������������������������������������������������������������������������
disable ; Turn off interrupts while enabling SCI
ldd #(0080h+QSMIARB)
std QMCR ; Set IARB=10 for intermodule bus arbitration
ldd #MY_QILR ; our QILR configuration
std QILR ;
ldd #BR9600 ; Set up 9600 baud rate
std SCCR0
ldd #RIE+RE+TE ; Receiver enabled with interrupts active,
; Transmitter enabled without interrupts,
; 1 Start Bit, 1 Stop Bit, 8 Data Bits
std SCCR1 ; Set up SCI operating conditions
rdclr:
ldd SCSR ; Get current status of SCI
bitb #RDRF ; Read receive data ready (RDR) until RDR reset
beq scirdy ; ZF=1 (RDRF=0), so no RDR is empty
ldab SCDR ; Read input data (a mechanism to reset RDRF)
bra rdclr ; Loop until clear
scirdy:
enable ; Turn interrupts back on
;*************** BEGIN **************
ldk #.__bss__ ; load extended address of stack
tbek
tbxk
tbyk
tbzk
ldx #sbss ; start of bss
clrd ; to be zeroed
bra mtest ; start loop
bcl:
std 0,x ; clear memory
aix #2 ; next word
mtest:
cpx #__memory ; end of memory ?
blo bcl ; no, continue
jsr _main ; call application
_exit:
bgnd ; loop here if return
1$:
bra 1$
;
.end
No comments:
Post a Comment