Thursday, September 30, 2004

Some Cool Geek's Sites

I got these links from some magazine (I guess it is MaximumPC). Some of them not that interesting, but some of them are cool!.

http://www.windowsupdate.com
http://www.arstechnica.com
http://www.slashdot.org
http://www.shocknews.com
http://www.theinqurer.net
http://www.penny-arcade.com
http://www.gizmodo.com
http://www.hyperdictionary.com
http://www.wikipedia.com
http://www.maximumpc.com/forums

Wednesday, September 29, 2004

Should I buy a new Flash Memory now?


Good question. Based on recent ads, the prices of flash memory have tumbled significantly compared to few months ago. One of online merchant I visited (www.tigerdirect.com) even offers $9.99 for 256 Kingston CompactFlash memory (I guess it is 1x speed).

Depends on your need, the price range can go from US $9.99 up to couple hundreds of dollars for the top memory (such as 4 GB, 40x speed). The speed plays a big role in pricing. The access speed (read/write) factor is similar to CD drive (150 KB/sec is for 1x speed, 300 KB/sec is for 2x speed so on). The new high speed CF sometimes is called CF II.

One thing I still hate to see is there are too many variants and different standard of flash memory. There is CompactFlash I/II, there is Memory stick, MemoryStick Pro, MemoryStick Duo, SmartMedia, SmartDigital, MM and what else, I don't remember. Why don't these people just make one single standard then our life would be better, isn't?

For people who are eager to see and compare the prices, check www.shopping.com, www.dealtime.com, www.mysimon.com, www.techbargains.com, or www.ebay.com. There are many other online shopping comparation portals but I cannot list them all here. Just search them at google, you will see many of them. Comments from previous buyers on these sites are many times useful. The more buyers put comments, the more confidence (or inassurance) you may get. Just check them out!
Point-to-Point Protocol

Introduction


The Point-to-Point Protocol (PPP) originally emerged as an encapsulation protocol for transporting IP traffic over point-to-point links. PPP also established a standard for the assignment and management of IP addresses, asynchronous (start/stop) and bit-oriented synchronous encapsulation, network protocol multiplexing, link configuration, link quality testing, error detection, and option negotiation for such capabilities as network layer address negotiation and data-compression negotiation. PPP supports these functions by providing an extensible Link Control Protocol (LCP) and a family of Network Control Protocols (NCPs) to negotiate optional configuration parameters and facilities. In addition to IP, PPP supports other protocols, including Novell's Internetwork Packet Exchange (IPX) and DECnet.



PPP Components

PPP provides a method for transmitting datagrams over serial point-to-point links. PPP contains three main components:

General Operation

To establish communications over a point-to-point link, the originating PPP first sends LCP frames to configure and (optionally) test the data link. After the link has been established and optional facilities have been negotiated as needed by the LCP, the originating PPP sends NCP frames to choose and configure one or more network layer protocols. When each of the chosen network layer protocols has been configured, packets from each network layer protocol can be sent over the link. The link will remain configured for communications until explicit LCP or NCP frames close the link, or until some external event occurs (for example, an inactivity timer expires or a user intervenes).

Physical Layer Requirements

PPP is capable of operating across any DTE/DCE interface. Examples include EIA/TIA-232-C (formerly RS-232-C), EIA/TIA-422 (formerly RS-422), EIA/TIA-423 (formerly RS-423), and International Telecommunication Union Telecommunication Standardization Sector (ITU-T) (formerly CCITT) V.35. The only absolute requirement imposed by PPP is the provision of a duplex circuit, either dedicated or switched, that can operate in either an asynchronous or synchronous bit-serial mode, transparent to PPP link layer frames. PPP does not impose any restrictions regarding transmission rate other than those imposed by the particular DTE/DCE interface in use.

PPP Link Layer

PPP uses the principles, terminology, and frame structure of the International Organization for Standardization (ISO) HDLC procedures (ISO 3309-1979), as modified by ISO 3309:1984/PDAD1 "Addendum 1: Start/Stop Transmission." ISO 3309-1979 specifies the HDLC frame structure for use in synchronous environments. ISO 3309:1984/PDAD1 specifies proposed modifications to ISO 3309-1979 to allow its use in asynchronous environments. The PPP control procedures use the definitions and control field encodings standardized in ISO 4335-1979 and ISO 4335-1979/Addendum 1-1979. The PPP frame format appears in Figure 13-1.


The following descriptions summarize the PPP frame fields illustrated in Figure 13-1:

The LCP can negotiate modifications to the standard PPP frame structure. Modified frames, however, always will be clearly distinguishable from standard frames.

PPP Link-Control Protocol

The PPP LCP provides a method of establishing, configuring, maintaining, and terminating the point-to-point connection. LCP goes through four distinct phases.

First, link establishment and configuration negotiation occur. Before any network layer datagrams (for example, IP) can be exchanged, LCP first must open the connection and negotiate configuration parameters. This phase is complete when a configuration-acknowledgment frame has been both sent and received.

This is followed by link quality determination. LCP allows an optional link quality determination phase following the link-establishment and configuration-negotiation phase. In this phase, the link is tested to determine whether the link quality is sufficient to bring up network layer protocols. This phase is optional. LCP can delay transmission of network layer protocol information until this phase is complete.

At this point, network layer protocol configuration negotiation occurs. After LCP has finished the link quality determination phase, network layer protocols can be configured separately by the appropriate NCP and can be brought up and taken down at any time. If LCP closes the link, it informs the network layer protocols so that they can take appropriate action.

Finally, link termination occurs. LCP can terminate the link at any time. This usually is done at the request of a user but can happen because of a physical event, such as the loss of carrier or the expiration of an idle-period timer.

Three classes of LCP frames exist. Link-establishment frames are used to establish and configure a link. Link-termination frames are used to terminate a link, and link-maintenance frames are used to manage and debug a link.

These frames are used to accomplish the work of each of the LCP phases.

Summary

The Point-to-Point Protocol (PPP) originally emerged as an encapsulation protocol for transporting IP traffic over point-to-point links. PPP also established a standard for assigning and managing IP addresses, asynchronous and bit-oriented synchronous encapsulation, network protocol multiplexing, link configuration, link quality testing, error detection, and option negotiation for added networking capabilities.

PPP provides a method for transmitting datagrams over serial point-to-point links, which include the following three components:

  • A method for encapsulating datagrams over serial links
  • An extensible LCP to establish, configure, and test the connection
  • A family of NCPs for establishing and configuring different network layer protocols

PPP is capable of operating across any DTE/DCE interface. PPP does not impose any restriction regarding transmission rate other than those imposed by the particular DTE/DCE interface in use.

Six fields make up the PPP frame. The PPP LCP provides a method of establishing, configuring, maintaining, and terminating the point-to-point connection.

Review Questions

Q—What are the main components of PPP?

A—Encapsulation of datagrams, LCP, and NCP.

Q—What is the only absolute physical layer requirement imposed by PPP?

A—The provision of a duplex circuit, either dedicated or switched, that can operate in either an asynchronous or synchronous bit-serial mode, transparent to PPP link layer frames.

Q—How many fields make up the PPP frame, and what are they?

A—Six: Flag, Address, Control, Protocol, Data, and Frame Check Sequence.

Q—How many phases does the PPP LCP go through, and what are they?

A—Four: Link establishment, link quality determination, network layer protocol configuration negotiation, and link termination.

Ubuntu Linux - Another Distro

another Linux distro coming. It is Ubuntu (unfamiliar with the name? me either, but sounds like an african language). Well, it is based on an african language but I forgot exactly what it means (something about "peace").

Anyway, not like other distros that use KDE, this distro comes with GNOME as its default desktop GUI. I have not tried GNOME desktop for a while, so I cannot comment about the latest GNOME.

For more detail, check this out: http://www.ubuntulinux.org/

Saturday, September 25, 2004

STI cell processor
Next generation processors


According to this website STI Cell Processor, a very sophisticated and advanced microprocessor is being jointly designed by 3 giant companies of microelectronics: Sony, Toshiba and IBM. The processor will be used for 21th century applications such as multimedia in living room, game console and other applications that may require broadband access.

The interesting thing from this story is that the broadband access will be more widely used in households not only for entertainment equipments, but also appliances such as smart microwave, smart refrigerator, or smart HVAC (Heat, Ventilation and Air Conditioning). This string of applications will definitely require a powerful microprocessor, not only for general computation as on PCs today but also for many real-time processes in embedded systems.

Many impressing nanoelectronic technology breakthroughs and inventions will be implemented on to this microprocessor. Among other things are SOI (Silicon on Insulator); 65-nm EUV (Extreme Ultra Violet) lithography; Cell architecture (similar to how human brain works); low-k (low dielectric) which means more silicon components (transistors, diodes, etc.) can be packed into a small die; copper wire.

This $400-million project will definitely change the way we think about a "PC" as the processor is considered as "supercomputer-on-a-chip". According to the site, the processor will even be more powerful than IBM's Big Blue supercomputer, one of the fastest computer in this universe. Not only because the processor will do Tera Floating Operation Per Seconds (Tera-FLOPS), but also because it will have about 20 "mini-cores" which work independently but in coherent and can be grouped all together programmably through software.

Another interesting part is that Sony will use this processor for its next generation game console, PS3. If we look at how amazing the NVidia 6800 Ultra performs but yet with much lower FLOPS compared to this Cell processor, you can imagine how good it can be with this "Tera FLOPS" Cell processor.

Utilizing massive data bandwidth and vast floating point capabilities, coupled with a parallel processing architecture, the Cell processor based development environment is expected to deliver quantum-leap innovation to entertainment applications. Cell-based workstations will be designed to expand the platform for creating digital content across future movie and video game entertainment industries.

Many applications, especially in multimedia and gaming, will be very boosted in performance by this chip. Video rendering processes which now might take hours, even days, can be done in minutes or even seconds. Ultra clear super surround sound, hyper-realistic 3D animation and other unimaginable possibilities and capabilities with current processors will be easily achieved by computers using these chips.

I believe the era of "WinTel" will soon dim, and new era of computing will shine. One thing I want to underline is that I believe the first operating system to support this chip is Linux. Believe me!

Tuesday, September 21, 2004

Confusing DRAM nomenclatures

Just figured out the different term for different kind of DRAM as listed in the following table:



















StandardSpeed/ClockName
DDR266 MHzPC2100
DDR333 MHzPC2700
DDR2400 MHzPC3200
DDR2533 MHzPC4200
DDR2675 MHzPC5400

Saturday, September 18, 2004

What is CORBA?

I just get started to learn more about this architecture. CORBA (Common Object Request Broker Architecture) is a new paradigm of interfacing clients to server(s). I just google it and found out there are many different packages for this, from commercieal packages such as Visibroker to open source ones.

Check this http://orbit-resource.sourceforge.net/ as one of them. It has many links related to ORB.
What is the Fastest Gaming PC in this year?

According to MaximumPC magazine, Alienware's Aurora ALX is the winner, followed closely by Falcon's Mach V. The Aurora is equipped with 2.6 GHz Athlon 64 FX-53 processor, ASUS A8V mobo, VIA K8T800 Pro chipset, 1 GB DDR400 (PC3200) RAM, GeForce 6800 Ultra VGA card, RAID0 HD, SB Audigy 2ZS audio card, 1 CD-RW, 1 DVD 2-layer writer. It is able to run a game like DOOM3 in 1280x1024 pixel resolution with 4AA enabled at 83.4 fps!

Wait a few more years as we see there are new technologies coming to these home PC, such as PCI Express (some mobos and video cards have already used this slot), new ATX form factor, dual or even multicore processors, Microsoft Longhorn OS. Not to mention GigE and Wi-Fi interfaces that some mobos have already used on their product lines.

Saturday, September 11, 2004

Build or just buy a prebuilt PC?

Just checked some computer makers' web sites, I've found out that pre-built PCs are cheaper to buy than buy the components separately and assembly them. For instance, a gaming PC 710G from Gateway.com is priced "only" $2000 equipped with Pentium4 3.2 GHz 800 MHz FB, 1 GB DDR-RAM, 250 GB SATA HD, 19" monitor, 256 MB NVidia GForce 5950G Ultra, SoundBlaster Audigy2, etc.

Friday, September 3, 2004










The chipset's designer did not comment, however, on the reasons for the PSP's delay. Sony has already said that the PSP will not ship in the U.S. until early 2005, and reports have surfaced that software makers don't believe the handheld will be released here until June 2005. Sony will ship the PSP in Japan later this year.



Not only will the PSP signal a new round in the console wars by challenging the established Nintendo Game Boy and new Nintendo DS, but the player will also begin the introduction of 3D-dedicated game into the handheld space.



The PSP will be based around four key blocks: the main CPU core, the media engine, the dedicated graphics processor, and the "Virtual Mobile engine," a reconfigurable assistant chip that will also be used in Sony's Walkman portable music player to conserve battery life. At press time, it wasn't clear whether each block would be integrated or broken out into a separate chip.



Some of the basic capabilities of the PSP player have already been disclosed. The game player will include a 4.3-inch widescreen TFT LCD, will contain a lithium-ion battery, and process AAC and MP3 music and AVC/@MP for pictures and movies. Games and other content will be stored on a 1.8-Gbyte UMD optical disc. The PSP is said to measure 70mm x 74mm x 23mm, and weigh 260 grams.




Sony PSP Game Processing Unit

In a presentation at the Hot Chips conference here Tuesday, designer Masanobu Okabe described further details of the PSP chipset, which the company concealed with the non-specific title: "A 90-nm embedded DRAM single-chip LSI with a 3D graphics H.264 codec engine and a reconfigurable processor".



Sony's PSP Embedded DRAM Specs
click on image for full view




Sony Computer Entertainment executives said in May that the PSP would be powered by a MIPS R4000 embedded CPU. Okabe said Tuesday that the CPU will run at speeds up to 333-MHz, with a bus that can run at speeds up to 166-MHz, depending upon the application load. In low-load situations, Okabe said, the chip will power down unused blocks. The entire chip will total 6 million gates and an undisclosed amount of transistors. Sony will fabricate the chip in a 7-layer, copper-enhanced 90-nanometer process.



Sony PSP System Chip Block Diagram
click on image for full view



To save power, the chip core's voltage will range between 0.8 and 1.2 volts. Okabe declined to disclose the average power consumption of the chip or the 3D engine, claiming that the power will vary depending on the application.



The host CPU block will also contain a security sub-block designed to protect data and help prevent hacking the PSP, its games, or the stored data.



Okabe's presentation of the I/O also contained some unexpected surprises. Early disclosures of the PSP indicated that the player would be capable of communicating via 802.11b WiFi. The only I/O functions Okabe described were USB 2.0 and Memory Stick, Sony's small-form-factor flash memory format.



Sony PSP Chip Summary
click on image for full view


The PSP's graphics engine will feature a 512-bit interface, Okabe said, pushing 664 million pixels or 35 million polygons per second. Freed from the need to conform to any other graphics API besides its own, Sony decided to support some basic graphics primitives as well as directional lighting, clipping, environment projection and texture mapping, fogging, alpha blending, depth and stencil tests, and dithering, all using either 16- or 32-bit color. The 166-MHz graphics core will include 2-Mbytes of embedded graphics memory.


Sony's PSP Embedded DRAM Specs
click on image for full view



Sony apparently will support a graphics model based on surfaces, rather than polygons. Okabe displayed an illustration of a cartoon character that looked more realistic than a polygon-based model, which he said contained the same amount of data. The graphics block will also be capable of vertex blending, a morphing technology that can interpolate changes made between objects.


Sony PSP Graphics Chip Specs
click on image for full view



"Small data size is advantageous to mobile data software," Okabe said.



Unfortunately, the purpose of the VME still remains a bit of a mystery. The reconfigurable logic will run at 166-MHz, and apparently reconfigure its internal 24-bit datapath in a single clock cycle, into configurations suited for H.264, a video algorithm based on MPEG-4, as well as game sounds and sound effects. Since the VME must be reconfigured for each operation, attendees here said they assumed that the PSP will not be able to combine video with external sound effects. However, Okabe said that the decoder would be the fastest found in any consumer-electronics device at the time of the PSP's launch.



Sony PSP Media Processing Unit
click on image for full view


Sony PSP Graphics Module Block Diagram
click on image for full view


Sony PSP Reconfigurable Virtual Mobile Engine
click on image for full view


Sony's VME Dissected
click on image for full view