Myths about NOR and NAND Flash

Myth 1: NAND Flash is slower than NOR.
The Reality: The performance characteristics of NAND Flash are: fast write (or program) speed , fast erase speed and medium read speed. This makes NAND Flash ideal for low cost, high density, high speed, program/erase applications. Read More Read More

Although NOR Flash offers a slight advantage in random read access times, NAND offers significantly faster program and erase times. For high performance data storage requirements, such as storing digital photos, downloading music and other advanced features popular in today's cell phones, the write/erase speeds of NAND provide a distinct performance advantage. This high performance is also what has made NAND Flash cards so widely used in data storage applications such as digital cameras.

Comparing the time required to perform a typical program and erase sequence for NOR and NAND Flash, for a 64KB erasable unit of memory, NAND outperforms NOR by a wide margin, at 17 milliseconds for NAND, and 2.4 seconds for NOR. In a system application, this difference is large enough to be easily noticed by the user. For the read function, the NAND performance is sufficient to support the system requirement, without a noticeable delay for the user.

Today, many designers build upon the conventional cell phone memory architecture by increasing density of the NOR and PSRAM, and adding NAND Flash to obtain greater performance and capacity for data storage.

Myth 2: NAND is not reliable
The Reality: Just as a hard disk drive is widely accepted with little concerns about bad sectors, NAND works in a similar way in that the controller maps around bad memory areas and error correction code (ECC) is used to correct bit errors. All controllers for NAND Flash have built-in ECC to automatically correct bit errors. Read More Read More

The industry standard is to correct any bit error to a level comparable to that of hard disk drives, or 10-14, which means one bit uncorrectable error every 10¹⁴ bits (12.5 terabytes). System designers have long been aware of the benefits of using ECC to detect and correct errors Historically, memory subsystems have used Hamming codee, ECC and Reed Solomon are common in hard drives and CDROMs.

Myth 3: NAND Flash is hard to integrate into a system.
The Reality: NAND Flash has an indirect or I/O-like access. Therefore, it must be accessed through a command sequence instead of through the direct application of an address to the address linesNAND Flash also has internal command, address and data registers. Today, a wide selection of NAND controllers and software drivers are available, making integration into a system relatively simple. Read More Read More

Although this interface may appear more cumbersome than the direct interface of NOR Flash, a notable advantage is the relative ease in upgrading to a higher density chip. Because of the indirect interface, the external pinout, or connection to the host, does not change with the density of the chip. This is similar to the hard disk drive interface in which different densities of hard disk drives could use the same cable interface.

Myth 4: MLC NOR is close to matching NAND capacities.
The Reality: The maximum available density currently available in MLC NOR Flash is 256Mb. The highest available capacity for MLC NAND Flash is currently 2Gb, and the highest available capacity for SLC NAND Flash is 1Gb. Read More Read More

A common method to increase the capacity of NOR Flash is to store multiple charge levels (typically four) enabling the storage of 2 bits in a memory cell, also known as Multi-level Cell (or MLC) NOR. However, by implementing MLC architecture, the effective speed is further reduced and write/erase endurance is also reduced.

Myth 5: MLC NAND won't hold up under extended use.
The Reality: MLC Flash has a different rating for the number of read/write cycles compared to SLC NAND Flash. Currently, SLC Flash is rated to have approximately 100,000 cycles and MLC Flash is rated to have approximately 10,000 cycles. However, if a 256MB MLC card can typically store 250 pictures from a 4-megapixel camera (a conservative estimate), its 10,000 read/write cycles, combined with wear-leveling algorithms in the controller, will enable the user to store and/or view approximately 2.5 million pictures within the expected useful life of the card. That number is so far beyond the average number of photos taken by the typical user that the difference in endurance is not significant for this application. Read More Read More

For those not familiar with the technology, MLC NAND Flash allows each memory cell to store two bits of information, compared to one bit-per-cell for SLC NAND Flash, resulting in a larger capacity and lower bit cost. While SLC NAND may be more appropriate for some specific applications, the difference will not affect the many common consumer applications, including most digital camera users. MLC NAND provides a very competitive level of performance and makes high density NAND cards more affordable, resulting in its growing popularity among consumers.

Myth 6: MLC NAND does not have the performance or endurance to reliably store your digital photos.
The Reality: MLC NAND is rated to have approximately 10,000 cycles, a level that is lower than SLC NAND, but more than sufficient to meet the needs of the vast majority of consumer users. A significant portion of the NAND Flash-based memory cards on the market today are made from MLC NAND, and the continuing rapid growth of this market can be considered an indication that the performance is meeting consumers' needs. Read More Read More

If a 256MB MLC card can typically store 250 pictures from a 4-megapixel camera (a conservative estimate), its 10,000 read/write cycles, combined with wear-leveling algorithms in the controller, will enable the user to store and/or view approximately 2.5 million pictures within the expected useful life of the card. That number is so far beyond the average number of photos taken by the typical user that the difference in endurance is not significant for this application.

Myth 7: MLC NAND does not have high enough performance for streaming video.
The Reality: The performance of MLC NAND is sufficient to support the 6 to 8 Mbits/second, transfer rate needed to store MPEG2 compressed video on a memory card. This works out to approximately 1MB/second. MLC NAND can transfer and write approximately 1.7MB/second.

Myth 8: SLC NAND is a generation ahead of MLC NAND.
The Reality: On Toshiba's roadmap, SLC development leads MLC by only two to three months. Presently, for each new generation, SLC chips are designed with MLC requirements in mind, so there is little lag-time between the two types of NAND. Read More Read More

The real issue is market acceptance, not actual time-to-market for the next generation. Currently, MLC development is well-timed to match market acceptance, with 512MB and 1GB cards widely available today to meet market demand.

Myth 9: The additional circuitry needed for MLC NAND takes up a significant amount of real estate.
The Reality: The circuitry required for MLC NAND is relatively minimal. A 4Gb MLC NAND Flash chip provides approximately 1.95 times greater density than a 2Gb SLC NAND chip. We believe that the more important question to the user is "what density can you get in a chip today?" Presently, the highest density MLC NAND Flash in production is 4Gb, whereas the highest density SLC NAND in mass production is 2Gb. The market demand for ever-higher densities of removable storage makes the lower-cost, higher density MLC card attractive to users and continues to enable new applications to emerge. Read More Read More

The rated storage capacity of 2Gb SLC NAND is 271MB, compared to 529MB for a 4Gb MLC NAND Flash chip, for a density increase of approximately 1.95 times greater.

Myth 10: NAND Flash is a slow storage technology.
The Reality: NAND Flash offers excellent performance for data storage. As a point of comparison, it can offer significantly faster performance and reliability than a hard disk drive, depending on the number and size of files transferred. For a random access of a 2kB file, a typical hard disk drive might take approximately 10ms to retrieve a file, while NAND Flash would take about 0.13ms to retrieve a similar size file. For a comparable write function with the 2kB file, NAND could be as much as 20 times faster. Because it is a solid state memory with no moving parts, NAND flash features a significantly shorter random access time compared to a mechanical hard disk drive.

Some Cool Geek's Sites

I got these links from some magazine (I guess it is MaximumPC). Some of them not that interesting, but some of them are cool!.

http://www.windowsupdate.com
http://www.arstechnica.com
http://www.slashdot.org
http://www.shocknews.com
http://www.theinqurer.net
http://www.penny-arcade.com
http://www.gizmodo.com
http://www.hyperdictionary.com
http://www.wikipedia.com
http://www.maximumpc.com/forums

Should I buy a new Flash Memory now?


Good question. Based on recent ads, the prices of flash memory have tumbled significantly compared to few months ago. One of online merchant I visited (www.tigerdirect.com) even offers $9.99 for 256 Kingston CompactFlash memory (I guess it is 1x speed).

Depends on your need, the price range can go from US $9.99 up to couple hundreds of dollars for the top memory (such as 4 GB, 40x speed). The speed plays a big role in pricing. The access speed (read/write) factor is similar to CD drive (150 KB/sec is for 1x speed, 300 KB/sec is for 2x speed so on). The new high speed CF sometimes is called CF II.

One thing I still hate to see is there are too many variants and different standard of flash memory. There is CompactFlash I/II, there is Memory stick, MemoryStick Pro, MemoryStick Duo, SmartMedia, SmartDigital, MM and what else, I don't remember. Why don't these people just make one single standard then our life would be better, isn't?

For people who are eager to see and compare the prices, check www.shopping.com, www.dealtime.com, www.mysimon.com, www.techbargains.com, or www.ebay.com. There are many other online shopping comparation portals but I cannot list them all here. Just search them at google, you will see many of them. Comments from previous buyers on these sites are many times useful. The more buyers put comments, the more confidence (or inassurance) you may get. Just check them out!

Point-to-Point Protocol

Introduction

The Point-to-Point Protocol (PPP) originally emerged as an encapsulation protocol for transporting IP traffic over point-to-point links. PPP also established a standard for the assignment and management of IP addresses, asynchronous (start/stop) and bit-oriented synchronous encapsulation, network protocol multiplexing, link configuration, link quality testing, error detection, and option negotiation for such capabilities as network layer address negotiation and data-compression negotiation. PPP supports these functions by providing an extensible Link Control Protocol (LCP) and a family of Network Control Protocols (NCPs) to negotiate optional configuration parameters and facilities. In addition to IP, PPP supports other protocols, including Novell's Internetwork Packet Exchange (IPX) and DECnet.

PPP Components

PPP provides a method for transmitting datagrams over serial point-to-point links. PPP contains three main components:

• A method for encapsulating datagrams over serial links. PPP uses the High-Level Data Link Control (HDLC) protocol as a basis for encapsulating datagrams over point-to-point links. (See Chapter 16, "Synchronous Data Link Control and Derivatives," for more information on HDLC.)
• An extensible LCP to establish, configure, and test the data link connection.
• A family of NCPs for establishing and configuring different network layer protocols. PPP is designed to allow the simultaneous use of multiple network layer protocols.

General Operation

To establish communications over a point-to-point link, the originating PPP first sends LCP frames to configure and (optionally) test the data link. After the link has been established and optional facilities have been negotiated as needed by the LCP, the originating PPP sends NCP frames to choose and configure one or more network layer protocols. When each of the chosen network layer protocols has been configured, packets from each network layer protocol can be sent over the link. The link will remain configured for communications until explicit LCP or NCP frames close the link, or until some external event occurs (for example, an inactivity timer expires or a user intervenes).

Physical Layer Requirements

PPP is capable of operating across any DTE/DCE interface. Examples include EIA/TIA-232-C (formerly RS-232-C), EIA/TIA-422 (formerly RS-422), EIA/TIA-423 (formerly RS-423), and International Telecommunication Union Telecommunication Standardization Sector (ITU-T) (formerly CCITT) V.35. The only absolute requirement imposed by PPP is the provision of a duplex circuit, either dedicated or switched, that can operate in either an asynchronous or synchronous bit-serial mode, transparent to PPP link layer frames. PPP does not impose any restrictions regarding transmission rate other than those imposed by the particular DTE/DCE interface in use.

PPP Link Layer

PPP uses the principles, terminology, and frame structure of the International Organization for Standardization (ISO) HDLC procedures (ISO 3309-1979), as modified by ISO 3309:1984/PDAD1 "Addendum 1: Start/Stop Transmission." ISO 3309-1979 specifies the HDLC frame structure for use in synchronous environments. ISO 3309:1984/PDAD1 specifies proposed modifications to ISO 3309-1979 to allow its use in asynchronous environments. The PPP control procedures use the definitions and control field encodings standardized in ISO 4335-1979 and ISO 4335-1979/Addendum 1-1979. The PPP frame format appears in Figure 13-1.

Figure 13-1: Six Fields Make Up the PPP Frame

The following descriptions summarize the PPP frame fields illustrated in Figure 13-1:

• Flag—A single byte that indicates the beginning or end of a frame. The flag field consists of the binary sequence 01111110.
• Address—A single byte that contains the binary sequence 11111111, the standard broadcast address. PPP does not assign individual station addresses.
• Control—A single byte that contains the binary sequence 00000011, which calls for transmission of user data in an unsequenced frame. A connectionless link service similar to that of Logical Link Control (LLC) Type 1 is provided. (For more information about LLC types and frame types, refer to Chapter 16.)
• Protocol—Two bytes that identify the protocol encapsulated in the information field of the frame. The most up-to-date values of the protocol field are specified in the most recent Assigned Numbers Request For Comments (RFC).
• Data—Zero or more bytes that contain the datagram for the protocol specified in the protocol field. The end of the information field is found by locating the closing flag sequence and allowing 2 bytes for the FCS field. The default maximum length
  of the information field is 1,500 bytes. By prior agreement, consenting PPP implementations can use other values for the maximum information field length.
• Frame check sequence (FCS)—Normally 16 bits (2 bytes). By prior agreement, consenting PPP implementations can use a 32-bit (4-byte) FCS for improved error detection.

The LCP can negotiate modifications to the standard PPP frame structure. Modified frames, however, always will be clearly distinguishable from standard frames.

PPP Link-Control Protocol

The PPP LCP provides a method of establishing, configuring, maintaining, and terminating the point-to-point connection. LCP goes through four distinct phases.

First, link establishment and configuration negotiation occur. Before any network layer datagrams (for example, IP) can be exchanged, LCP first must open the connection and negotiate configuration parameters. This phase is complete when a configuration-acknowledgment frame has been both sent and received.

This is followed by link quality determination. LCP allows an optional link quality determination phase following the link-establishment and configuration-negotiation phase. In this phase, the link is tested to determine whether the link quality is sufficient to bring up network layer protocols. This phase is optional. LCP can delay transmission of network layer protocol information until this phase is complete.

At this point, network layer protocol configuration negotiation occurs. After LCP has finished the link quality determination phase, network layer protocols can be configured separately by the appropriate NCP and can be brought up and taken down at any time. If LCP closes the link, it informs the network layer protocols so that they can take appropriate action.

Finally, link termination occurs. LCP can terminate the link at any time. This usually is done at the request of a user but can happen because of a physical event, such as the loss of carrier or the expiration of an idle-period timer.

Three classes of LCP frames exist. Link-establishment frames are used to establish and configure a link. Link-termination frames are used to terminate a link, and link-maintenance frames are used to manage and debug a link.

These frames are used to accomplish the work of each of the LCP phases.

Summary

The Point-to-Point Protocol (PPP) originally emerged as an encapsulation protocol for transporting IP traffic over point-to-point links. PPP also established a standard for assigning and managing IP addresses, asynchronous and bit-oriented synchronous encapsulation, network protocol multiplexing, link configuration, link quality testing, error detection, and option negotiation for added networking capabilities.

PPP provides a method for transmitting datagrams over serial point-to-point links, which include the following three components:

• A method for encapsulating datagrams over serial links
• An extensible LCP to establish, configure, and test the connection
• A family of NCPs for establishing and configuring different network layer protocols

PPP is capable of operating across any DTE/DCE interface. PPP does not impose any restriction regarding transmission rate other than those imposed by the particular DTE/DCE interface in use.

Six fields make up the PPP frame. The PPP LCP provides a method of establishing, configuring, maintaining, and terminating the point-to-point connection.

Review Questions

Q—What are the main components of PPP?

A—Encapsulation of datagrams, LCP, and NCP.

Q—What is the only absolute physical layer requirement imposed by PPP?

A—The provision of a duplex circuit, either dedicated or switched, that can operate in either an asynchronous or synchronous bit-serial mode, transparent to PPP link layer frames.

Q—How many fields make up the PPP frame, and what are they?

A—Six: Flag, Address, Control, Protocol, Data, and Frame Check Sequence.

Q—How many phases does the PPP LCP go through, and what are they?

A—Four: Link establishment, link quality determination, network layer protocol configuration negotiation, and link termination.

Ubuntu Linux - Another Distro

another Linux distro coming. It is Ubuntu (unfamiliar with the name? me either, but sounds like an african language). Well, it is based on an african language but I forgot exactly what it means (something about "peace").

Anyway, not like other distros that use KDE, this distro comes with GNOME as its default desktop GUI. I have not tried GNOME desktop for a while, so I cannot comment about the latest GNOME.

For more detail, check this out: http://www.ubuntulinux.org/

STI cell processor
Next generation processors

According to this website STI Cell Processor, a very sophisticated and advanced microprocessor is being jointly designed by 3 giant companies of microelectronics: Sony, Toshiba and IBM. The processor will be used for 21th century applications such as multimedia in living room, game console and other applications that may require broadband access.

The interesting thing from this story is that the broadband access will be more widely used in households not only for entertainment equipments, but also appliances such as smart microwave, smart refrigerator, or smart HVAC (Heat, Ventilation and Air Conditioning). This string of applications will definitely require a powerful microprocessor, not only for general computation as on PCs today but also for many real-time processes in embedded systems.

Many impressing nanoelectronic technology breakthroughs and inventions will be implemented on to this microprocessor. Among other things are SOI (Silicon on Insulator); 65-nm EUV (Extreme Ultra Violet) lithography; Cell architecture (similar to how human brain works); low-k (low dielectric) which means more silicon components (transistors, diodes, etc.) can be packed into a small die; copper wire.

This $400-million project will definitely change the way we think about a "PC" as the processor is considered as "supercomputer-on-a-chip". According to the site, the processor will even be more powerful than IBM's Big Blue supercomputer, one of the fastest computer in this universe. Not only because the processor will do Tera Floating Operation Per Seconds (Tera-FLOPS), but also because it will have about 20 "mini-cores" which work independently but in coherent and can be grouped all together programmably through software.

Another interesting part is that Sony will use this processor for its next generation game console, PS3. If we look at how amazing the NVidia 6800 Ultra performs but yet with much lower FLOPS compared to this Cell processor, you can imagine how good it can be with this "Tera FLOPS" Cell processor.

Utilizing massive data bandwidth and vast floating point capabilities, coupled with a parallel processing architecture, the Cell processor based development environment is expected to deliver quantum-leap innovation to entertainment applications. Cell-based workstations will be designed to expand the platform for creating digital content across future movie and video game entertainment industries.

Many applications, especially in multimedia and gaming, will be very boosted in performance by this chip. Video rendering processes which now might take hours, even days, can be done in minutes or even seconds. Ultra clear super surround sound, hyper-realistic 3D animation and other unimaginable possibilities and capabilities with current processors will be easily achieved by computers using these chips.

I believe the era of "WinTel" will soon dim, and new era of computing will shine. One thing I want to underline is that I believe the first operating system to support this chip is Linux. Believe me!